Associate Prof. Jiang Li Won the Early Career Award on the 8th China Fault Tolerant Computing Conference

Released Time: 2019-08-22

From Aug 15 to 17, the 8th China Fault Tolerant Computing Conference (CFTC 2019) was held in Beijing. It was hosted by China Computer Federation (CCF) and organized by the technical committee of fault tolerant computing of CCF, Tsinghua University and Beijing Qidiqingyun Intelligent Energy Co. Ltd. 

The conference was themed on “fault-tolerance escorting the development of hard science and technology”. There was an extensive and in-depth academic exchange on hard science and technology in the fields of chips, software and systems. More than 500 people from academia and industry attended the conference. At this conference, a number of hot issues in the field of integrated circuits were discussed, including chip security, open-source EDA and agile development based on open-source IP, storage fault tolerance and storage computing. These issues are crucial to changing the situation that our EDA for chip design are lagging behind and the talent of integrated circuit design are scares, therefore crucial to breaking the blockade on techniques by the US and escorting the development of hard science and technology. 

One of the highlights of the conference was the unveiling of this year's CCF Integrated Circuit Early Career Award. The award is aimed to provide support for the early career of young scholars in the field of integrated circuits with less than 6 years’ working experience. It is the only professional award for integrated circuit in the CCF system, and this year is the second year.

After three rounds of review by seven international and domestic experts, associate Prof. Jiang Li of Shanghai Jiao Tong University was awarded the honor for his academic contributions in the field of fault tolerant design for IC test in the post-Moore era.

Jiang Li has been focusing on the research of IC test and fault-tolerant technology. Addressing the problem of the high cost of 3D chip, he first proposed the architecture design and optimization method of 3D chip "pre-binding test", which was introduced into IEEE standard P1838. In view of the high failure rate of TSV in 3D IC, a highly efficient TSV repair architecture and the technology of sharing redundant resources on adjacent chips in 3d memory are designed, which set a new record of the repair efficiency of 3D memory.


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